Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element

The delay element is considered a very important component in various systems such as microprocessors, memories, and delay-locked loops, to name such a few. Most of these applications require that the delay element be tunable. In this paper, a tunable delay element is proposed. This delay element is based on MOS transistors only and has both fine and coarse tuning. The design procedure of the proposed delay element is also presented with compact-form expressions derived for the delay offset, the delay resolution, and the tuning range in terms of technology-dependent parameters and the control-word length. These expressions are verified by comparison with the simulation results. The various trade-offs involved in the design process are discussed. The proposed delay element is verified by simulation using the 45 nm CMOS predictive technology model (PTM). The monotonicity of the proposed delay element is guaranteed and various performance metrics of this delay element are compared with their corresponding metrics in previously proposed delay elements. A delay resolution of 2.2 ps and a tuning range of 357.5 ps are achieved with an average power consumption of 0.85 μW for three bits at 1 GHz. The estimated silicon area is 0.247 μm2. Finally, the application of the proposed delay element as a digitally controlled ring oscillator (DCRO) is presented and investigated.