Optimum sizing of the sleep transistor in MTCMOS technology

Multi-threshold voltage complementary metal-oxide semiconductor (MTCMOS) technology finds a wide variety of applications in reducing the subthreshold-leakage current in both combinational and sequential circuits. This is due to the fact that slightly increasing the threshold voltage causes a dramatic decrease in the subthreshold-leakage current. One of the most important applications of the MTCMOS technology is the use of a sleep transistor with high threshold voltage. However, the decision on the sizing of the sleep transistor is a critical issue because there are various trade-offs that the designer must face with this respect. In this paper, the area, the static and dynamic-power consumption, and the time delay are investigated with respect to the aspect ratio of the sleep transistor with compact-form expressions derived for them. Accordingly, the optimal size of the sleep transistor is determined quantitatively. In addition, a realistic figure of merit (FOM) that takes into account the contradicting parameters when sizing the sleep transistor is introduced and verified by simulations. The results are discussed for various cases of the logic circuit at hand. The results obtained are also verified by simulation adopting the Berkeley predictive technology model (BPTM) of the 45 nm, 32 nm, and 22 nm CMOS technologies with power-supply voltages, VDD, equal to 1 V, 0.9 V, and 0.8 V, respectively.